C-DAC invites Applications for the post of Director General

Centre for Development of Advanced Computing (C-DAC), is a Scientific Society of the Department of Information Technology, Ministry of Communications and Information Technology, Govt.of India. C-DAC's areas of expertise range from R&D work in Foundation Technologies to Product Development, IP Generation and Technology Transfer, Deployment of Solutions in various sectors directly or through partnership model, High Performance Computing and Grid Computing; Language Computing & Speech Processing; Computer Science & Software Technologies including Free & Open Source software; and Professional Electronics including Embedded Systems, Platforms, Specialized Hardware, Broadband and Wireless Control Systems & Cyber-Security. On the applications and solutions side, the prominent sectors include Science & Engineering, e-Governance, Health, Education, Power, Railways, Industry among others. Education & Training Programmes focused on high and specialized technical courses and finishing school type modules of relevance to industry. Applications are invited for the post of Director General for Centre for Development of Advanced Computing (C-DAC) in HAG 67000-(annual increment @ 3%)-79000 (pre-revised pay scale: Rs.22400-525-24500) and it is proposed to be filled by Direct Recruitment /Absorption / Deputation basis. The Director General shall be the Chief Executive of C-DAC and shall have administrative and financial powers to implement decisions of the Governing Council (GC)/ Coordination Committee (CC) of C-DAC, evolve strategies and plans for proper management of C-DAC and shall make proposals to the CC / GC regarding Staff Rules, Service Conditions etc. of C-DAC. Method of Recruitment: Direct Recruitment / Absorption / Deputation. The appointment would be for a tenure not exceeding five years or till date of retirement on superannuation, whichever is earlier, provided that, in case of appointment on Deputation, the date of superannuation will be as applicable in the lending organization.

Direct Recruitment : Essential Educational Qualifications & Experience B.E. / B.Tech. in relevant discipline* with 25 years experience. Or Post-Graduate in Engineering in relevant discipline* with 20 years experience. Or Ph.D. with over 15 years of relevant experience*. * Relevant Discipline / Experience: Computer Science / Electronics / Electrical / IT/ Telecommunication. Absorption / Deputation Basis : In case of absorption / deputation - officers of the Central/State Govt. / PSUs / Autonomous Bodies: holding analogous post on regular basis. Or Having 5 years of regular service in the scale of pay of Rs.18400-500-22400 (pre-revised) Possessing the qualifications prescribed for direct recruitment. Age Limit for Direct Recruits : Preferably below 50 years for Direct Recruitment and 56 years for Deputation / Absorption (Relaxation can be given in deserving cases). The age will be as on the last date of receipt of applications. Job Responsibilities : The Director General will be responsible for overall management and running of C-DAC under the overall guidance of Governing Council. Director General shall be the Ex-Officio Member of the Governing Council. The Director General shall exercise such executive and financial powers as contained in C-DAC charter or delegated to him by the Governing Council. The Director General may delegate some of his powers, functions and duties to subordinate levels. Job Requirements: The ability to guide, motivate, harness and lead a group of highly specialized and talented pool of scientific, R&D, technical and administrative personnel towards achievement of institutional goals. The ability to independently manage an organization of high repute and national importance including aspects such as manpower planning, development, budgets, finance and various other organizational aspects. A broad scientific, R&D and technological vision and ability to keep track of recent trends and emerging developments in the relevant technology field. In-depth exposure and sound knowledge of Intellectual Property Rights (IPR) and commercial aspects of high-end research. The ability to effectively interface with the Government, academic, R&D and educational institutions and the IT industry. Experience in heading and delivering significant R&D projects in the area of High Performance Computing (HPC) / Grid Computing / Information Technology / Software Technology / Telecommunications / VLSI Design etc. Desirable Requirements: Ph.D. in Computer Science / Computer Engineering from a recognized University or institution and should be capable of guiding Post Graduate / Doctorate degree students in Computer Science / Computer Engineering. Proven track record and experience in leading and delivering significant R&D projects in the areas of High Performance Computing (HPC), Grid Computing, Information Technology, Software Technology, Telecommunications, VLSI Design etc. Must have to his credit national and international publications and acclaimed research contributions. Experience in dealing with projects involving foreign collaboration and liaison with Government Departments and Industry. High visibility in professional and academic circles and should have been involved and contributed to national and international consultative / advisory committees. How to Apply: Candidates meeting the above eligibility requirements may send in their applications complete in all respects in the prescribed format along with the detailed resume and attested copies of certificates relating to qualifications, relevant experience, date of birth, etc., by the last date prescribed to The Director, ABC Division, Department of Information Technology, 6, CGO Complex, Electronics Niketan, Lodhi Road, New Delhi - 110 003. To download Application Form visit http://www.cdac.in/html/jobs/dg03122009.pdf Persons working in Government/PSUs/Autonomous bodies may send their application through proper channel, along with photocopies of ACRs of the last five years duly attested by an officer not below the rank of Under Secretary or equivalent and vigilance/disciplinary clearance. The integrity of the officer may also be certified along with a certificate that no minor / major penalty has been imposed on him. Last date of receipt of applications: 22nd February, 2010. Note:  Applications which are not in conformity with the requirement indicated in the advertisement are liable to be rejected.  Only short-listed candidates will be called for interview. Mere fulfilling of requirement as laid down in the advertisement does not qualify a candidate to be called for interview.

Immediate Openings for HITEC Vertical Hyd & Blr- Infotech Enterprises Ltd

WLAN Engineers-Sr.Engineers/Leads:

• 3-7 yrs of experience with expertise in WinCE/REX/Nucleus/WinMobile/Linux.
•  Expertise with SDIO/SPI buses, Experience working with Wi-Fi and networking drivers and TCP/IP in general.
• Experience various cell phone platforms such as Qcom, TI, Infineon etc.
• Device Driver Development and Porting of Stacks, Middleware/frameworks.
• Ability to understand client driver, tools and API libraries and be able to port it to the customer’s platform. 
• Understanding of Network Layer 3 down to Layer 1, specifically hardware centric expertise with strong knowledge of device driver, kernel mode driver and bus interfaces like SDIO. 
• Candidates should be able to quickly understand the customer’s platform and requirements. Need to interact with clients in understanding the requirements.

Job Location: Bangalore

Experience: 3 to 7 yrs

Qualification: Diploma/B.Tech/M.Tech/MCA/MSC.

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Semi Engineers-Sr.Engineers/Lead

• 3-7 yrs of experience with expertise in  WinCE/WinMobile/Linux OS 
• Experience in Pre and Post silicon Development environment, OS porting and bring up on emulators, simulators and development boards.
• Hands on Board Support Package (BSP), Hardware Diagnostic Applications development.
• Good knowledge of System internals of an OS – Linux, Windows
• Device drivers development expertise – USB, PCI, UART, KB, Touch Screen, Connectivity bus  controllers, Timers and DMA

Audio – Audio controller drivers

Video – Display/Video controller drivers

·         Exposure to Device Driver Development and Porting of Stacks, Middleware/frameworks.

·         OS internals : Kernel , File system

• Need to interact with clients in understanding the requirements and should be able to architect solutions.
• Complete understanding of the overall system, interactions among various modules/blocks in the system.
• Working experience with standard body forums and communities.
• Should be able to understand the technology landscape, have understanding of current limitations and challenges.

Job Location: Bangalore

Experience: 3 to 7 yrs

Qualification: Diploma/B.Tech/M.Tech/MCA/MSC.

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Physical Design - Sr.Engineers/Leads:

• 4-7 yrs of exp in Physical Design of which min 2.5+ years of experience in Magma place and route tool (talus is a plus).
• Able to write Magma Tcl scripts. Very good experience in Clock tree Synthesis involving multiple clocks.
• Should be able to analyze the reports in different timing modes & come up with solutions. Good knowledge of floorplanning, congestion with more than 20-25 memories.
• Good Understanding of command scripts like fixcell, fixtime & ability to modify & change it to suit the design requirements.
• Good understanding of Primetime & ability to implement ECOs in Magma (PTSI is a plus).
• Must have a good knowledge of STA analysis. Have worked on lower technologies 65nm & below.
• Very good knowledge of Physical verification (DRC/LVS/Antennas) tool such as Calibre. Good analytical & adaptation skills. 

Job Location: Bangalore/Hyderabad

Experience: 4 to 7 yrs

Qualification: Diploma/B.Tech/M.Tech

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

DFT - Sr.Engineers/Leads:

• 4-8 yrs exp in DFT with Logic Vision tools is mandatory.
• Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
• Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
• Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
• Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
• Experience in Gate Level Simulations, Synthesis, STA and Formal Verification.
• Understanding of ATE and test engineering. Post-Silicon debug.
• Programming in Perl, tcl, awk and c/c++    

Job Location: Bangalore/Hyderabad

Experience: 4 to 8 yrs

Qualification: Diploma/B.Tech/M.Tech

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

ASIC Design- Sr.Engineers/Leads:

• 5-9 yrs of exp in ASIC Design with following skill set:
• Expertise in RTL Coding - Verilog/VHDL and exposure to DFT skill set.
• Strong scripting skills - PERL/TCL.
• Should have worked on 65nm or lower node multi-million gate tape outs.
• Experience in closing timing on DDR2/DDR3/PCIE interfaces and expertise in cross-talk analysis and repair.
• Expertise in Physical Design with focus on clock trees at block and chip level.
• Should mentor and guide ASIC design engineers.
• He/She will be responsible for full chip synthesis, writing constraints interfacing with logic design engrs, implementing low power synthesis techniques, timing and SI closure of blocks and full chip.
• Working with the Physical Design teams, clock tree synthesis strategy for block level as well as chip level, timing closure on DDR2/DDR3/PCIE etc., interfaces, running multi-corner-multi-mode STA, cleaning up constraints working with logic design and DFT teams.

Job Location: Hyderabad

Experience: 5 to 9 yrs

Qualification: Diploma/B.Tech/M.Tech

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Custom Layout - Sr.Engineers/Leads:

• 4-7yrs of exp. in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC
• Strong Layout Design Concepts.
• Experience in Pcell development, maintaining and modifying PDKs
• Experience in Layout Design tools such as Virtuoso, Virtuoso-XL.
• Exposure to digital place & route, expertise in SKILL Programming Language
• Experience in Physical verification and exposure to Calibre, Hercules and Assura.
• He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout, physical verification, maintaining PDKs, evaluating them.
• The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO.

Job Location: Bangalore/Hyderabad

Experience: 4 to 7 yrs

Qualification: Diploma/B.Tech/M.Tech.

Note:  

ð  Interested candidates resumes can be routed to Mr.Vijay kumar Mavurappu @vijay.mavurappu@infotech-enterprises.com

ð  For more information you can guide them to visit us @ www.infotech-enterprises.com